1. Field of the Invention
The present invention relates to the formation of contacts and runners in semiconductor devices. More particularly, the present invention relates to a dual damascene metallization method used in the formation of semiconductor devices utilizing a silicon hard mask to minimize thickness of resist material required to form contacts and runners in the semiconductor devices.
2. State of the Art
Two exemplary methods of fabricating contacts and runners for integrated circuits are damascene and dual damascene techniques. The damascene technique is an interconnection fabrication process in which runner trenches are formed in an insulating or dielectric layer of a semiconductor device. The runner trenches are then filled with metal or other conductive material to form conductive lines, known as xe2x80x9crunners.xe2x80x9d The dual damascene technique is a multilevel interconnection fabrication process in which, in addition to forming runner trenches, contact openings are formed in the insulating or dielectric layer of the semiconductor device. The runner trenches and the contact openings are then simultaneously filled with conductive material to form both the runners and contacts.
An exemplary dual damascene technique for forming a memory cell includes providing an intermediate structure including a substrate having active areas electrically isolated by field oxide areas. The isolated active areas have drain regions and source regions doped into the substrate. Transistor gate members are formed on the surface of the substrate, including gate members residing on substrate active areas spanned between the drain regions and the source regions, and further including gate members residing on the thick field oxide. An insulating layer covers the transistor gate members and the substrate. The insulating layer is patterned with a first resist material such that the patterned first resist material has a plurality of openings located in desired positions for forming contact openings. The insulating layer is then anisotropically etched through the openings in the first resist material to expose the source regions and the drain regions in the underlying substrate. The first resist material is then removed and the insulating layer is coated with a second resist material which is patterned with the image pattern of the desired runners in alignment with the contact openings. The insulating layer is anisotropically etched to form runner trenches in an upper portion of the insulating material. After the runner trench etching is complete, both the contact openings and runner trenches are filled with metal or other conductive material, thereby forming the contacts and the runners. The dual damascene technique is an improvement over the single damascene technique because the dual damascene fills both the contact openings and the runner trenches with conductive material at the same time, thereby eliminating process steps for filling the contact openings and runner trenches separately. The dual damascene technique may also be used for forming multilevel signal lines in the insulating layers of a multilayer substrate on which various semiconductor devices reside.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. However, as components become smaller and smaller, tolerances for all semiconductor structures (such as circuitry runners, contacts, and the like) become more and more stringent. Although the reduction in size creates technical problems, the future advancement of the technology requires the capability for forming sub-0.35 xcexcm contact openings with aspect ratios (height to width) as high as 10 to 1.
An exemplary technique employed in forming high aspect ratio structures is MERIE (magnetically enhanced reactive ion etch). For example, if a 3 micron (30 kxc3x85) deep contact opening in an insulating layer, such as BPSG (borophosphosilicate glass), is desired, a layer of resist material having a thickness of at least about 11 kxc3x85 to 14 kxc3x85 is necessary. Such a thickness of resist material is required because as the insulating layer is etched in the MERIE system, the resist material is also ablated away. Thus, the resist material must be thick enough not to ablate completely away during the etching of the contact opening in the insulating layer. If the resist material is ablated away, the MERIE will damage (i.e., etch) the top surface of the insulating layer. Unfortunately, the thicker the resist material, the more difficult it is to form contact openings. More specifically, the depth of focus is reduced as resist thicknesses increase, therefore reducing the reproducible resolution obtainable in the photolithography step. Thus, the best pattern resolution is obtained with thinner photoresists. If the patterned images (e.g., by lithography) are not well defined (which occurs with a thick resist layer), the etching of the contact opening in the insulating layer slows down or stops before reaching the substrate. Thus, no contact can be made with the source or drain regions on the substrate. In order to insure complete etching of the contact opening, the thickness of the resist material can be reduced (for example down to about 8 kxc3x85 to 10 kxc3x85) or the chemistry (chemicals used in the MERIE system) can be changed to run with a specific chemistry that results in less polymerizing (i.e., less polymer-rich chemistry which means a lower resist material selectivity). The xe2x80x9clowerxe2x80x9d polymerizing etches generally can etch deeper for a given contact size than xe2x80x9chigherxe2x80x9d polymerizing etches, which tend to form more sidewall polymer, eventually sealing the contact shut during the etch. With either option, the resist material will likely be ablated away before completion of the etching of the contact opening in the insulating material. Another option is to increase the diameter of the contact opening. However, this would decrease the aspect ratio which is, of course, counter to the goal of semiconductor miniaturization.
Therefore, it would be advantageous to develop a technique for forming high aspect contacts for semiconductor devices which minimizes the thickness of resist material required in the formation of the same, while using inexpensive, commercially available, widely practiced semiconductor device fabrication techniques and equipment without requiring complex processing steps.
The present invention relates to forming a silicon hard mask to act as a potential etch stop between a patterned resist layer and a buffer or insulator layer in the fabrication of structures, such as contacts, for semiconductor devices. The present invention may also be used in a dual damascene metallization method in the formation of contacts and runners in semiconductor devices.
The most fundamental method aspect of the present invention involves forming a contact in a barrier layer which covers an active element (such as a conductive material or metal trace, source region or a drain region doped in a silicon substrate, or the like) of a semiconductor device. A silicon hard mask, such as an amorphous silicon (xe2x80x9ca-Sixe2x80x9d) or polymeric silicon (xe2x80x9cpoly-Sixe2x80x9d) layer, is deposited over the barrier layer. A resist layer is then patterned on the silicon hard mask. The silicon hard mask and barrier layer are etched to form a contact opening. The silicon hard mask acts as a backup to the resist layer. The silicon hard mask prevents the potential etching of the barrier layer, which is protected by the first resist layer, by acting as an etch stop if the first resist layer is ablated away during the etching of the contact openings. If such a silicon hard mask is not used, the resist layer must be thicker in order to ensure that the resist layer is not ablated away during the etching of the contact openings. However, as noted previously, if the resist layer is too thick, the etching of the contact opening in the barrier layer slows down or stops before reaching the substrate. Thus, no contact can be made with the active element.
Any remaining resist layer is stripped, and a layer of silicidable metal and, optionally, a barrier film are deposited respectively over the etched structure to form a layered structure. The layered structure is then annealed to form a mask silicide layer by the reaction of the silicidable metal with the silicon hard mask. The mask silicide layer is much more conducive to abrasive removal, such as by chemical mechanical planarization (CMP), than a hard silicon mask.
Additionally, if the contact opening is formed to a silicon-containing substrate, the annealing forms contact silicide layers in the bottoms of the contact openings by the reaction of the silicidable metal with the silicon of the substrate. The contact silicide layers are generally formed to reduce the contact resistance at the interface between the conductive material to be subsequently deposited in the contact openings and semiconductor device drain regions and the source regions formed in the substrate material.
A conductive material is deposited to fill the contact openings and an upper portion of the conductive material and the mask silicide layer are removed, preferably using an abrasive process, such as CMP, to form the contact. It is, of course, understood that the mask silicide layer can optionally be removed prior to filling the contact openings with conductive material.
Another method of the present invention is practiced after the formation of an intermediate structure comprising transistor gates on a silicon substrate which has been oxidized to form thick field oxide areas to electrically isolate active areas on the silicon substrate and which has been exposed to implantation processes to form drain and source regions. The intermediate structure further comprises at least one barrier layer which covers the transistor gates and the silicon substrate. An etch stop layer is formed over the barrier layer and a dielectric layer is formed over the etch stop layer. A silicon hard mask, such as an amorphous silicon (xe2x80x9ca-Sixe2x80x9d) or polymeric silicon (xe2x80x9cpoly-Sixe2x80x9d) layer, is deposited over the dielectric layer. A first resist layer is patterned on the silicon hard mask and the silicon hard mask is etched to form intermediate contact openings. The dielectric layer, the etch stop layer, and the barrier layer are then etched through intermediate contact openings to expose the drain regions and/or the source regions and form contact openings.
Again, the silicon hard mask acts as a backup to the first resist layer. The silicon hard mask prevents the potential etching of the dielectric layer, the etch stop layer, and the barrier layer (which is protected by the first resist layer) by acting as an etch stop if the first resist layer is ablated away during the etching of the contact openings. As discussed above, if such a silicon hard mask is not used, the first resist layer must be thicker in order to ensure that the first resist layer is not ablated away during the etching of the contact openings. However, if the first resist layer is too thick, the etching of the contact opening slows down or stops before reaching the substrate. Thus, no contact can be made with the source or drain regions on the substrate.
If the silicon hard mask technique of the present invention is used in a dual damascene method, runners are formed after the contact opening is formed. First, any remaining first resist layer is stripped and a second resist layer is patterned on the silicon hard mask in a pattern of desired runners. A portion of the second resist layer deposits in the contact openings to cover and protect the drain regions and the source regions. The silicon hard mask is etched to form intermediate runner trenches. The dielectric layer and the etch stop layer are then etched to form runner trenches. Any remaining second resist layer is then stripped to form an etched structure. A layer of silicidable metal and a barrier film are deposited respectively over the etched structure to form a layered structure.
The layered structure is then annealed to form contact silicide layers in the bottom of the contact openings by the reaction of the silicidable metal with the silicon in drain regions and source regions. Additionally, the annealing forms a mask silicide layer by the reaction of the silicidable metal with the silicon hard mask. The mask silicide layer is much more conducive to abrasive removal, such as by CMP, than a hard silicon mask.
A conductive material is deposited to fill the contact openings and the runner trenches (if a dual damascene method is used). An upper portion of the conductive material and the mask silicide layer are removed. The removal of the upper portion of the conductive material and the mask silicide layer effectuates the separation of the conductive material within the contact openings and the runner trenches to form capacitor contacts (in electrical communication with the drain regions), bitline contacts (in electrical communication with the source regions), and/or runners (if a dual damascene method is used).
The use of the silicon hard mask of the present invention results in a substantial reduction of the required thickness of the resist material. For the etching of a 30 kxc3x85 deep contact opening, the thickness of the resist material layer may be reduced from between about 11 kxc3x85 and 14 kxc3x85 to between about 7 kxc3x85 and 9 kxc3x85. For the etching of a 5 kxc3x85 deep runner trench, the thickness of the required resist material layer may be reduced from between about 5 kxc3x85 and 7 kxc3x85 to between about 2 kxc3x85 and 3 kxc3x85.